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DTC, Design Technology Center
[專題演講] 9/11 PM 3:00 -- Dr. Erik Jan Marinissen(IMEC): 3D IC Stacking: DIY Short Course

     3D IC Stacking: DIY Short Course

Erik Jan Marinissen

  IMEC – Leuven, Belgium
  TU Eindhoven – Eindhoven, the Netherlands

  Date: September 11, 2017
  Location: 304R Delta Bldg.


Three-dimensional stacking of ICs have kept the communities in both technology and design research busy for several years now. No wonder, because 3D-SICs hold the promise of heterogeneous integration, inter-die connections with increased performance at lower power dissipation, and increased yield and hence decreased product cost. In this presentation, we will introduce the main 3D-SIC components and build on those an ultra-short course on 3D stack architecting. The 3D benefits can only materialize if 3D-SICs can be properly tested for manufacturing defects. Recently, the test community has started to work on test solutions for these IC products, signaling that their high-volume market introduction is now imminent.



Erik Jan Marinissen is Principal Scientist at the world-renowned research institute imec in Leuven, Belgium, where he is responsible for the research on test and design-for-test, covering topics as diverse as TSV-based 3D-stacked ICs, silicon photonics, CMOS technology nodes below 10nm, and STT-MRAMs. In addition, he is Visiting Researcher at Eindhoven University of Technology, the Netherlands. Previously, he worked at NXP Semiconductors and Philips Research Laboratories in Eindhoven. Marinissen holds an MSc degree in Computing Science (1990) and a PDEng degree in Software Technology (1992), both from Eindhoven University of Technology. He is (co-)author of 250 journal and conference papers and (co-) inventor on fifteen granted US/EP patent families. Marinissen is recipient of the Most Significant Paper Awards at ITC 2008 and ITC 2010, Best Paper Awards at the Chrysler-Delco-Ford Automotive Electronics Reliability Workshop 1995 and the IEEE International Board Test Workshop 2002, the Most Inspirational Presentation Award at the IEEE Semiconductor Wafer Test Workshop 2013, the HiPEAC Tech Transfer Award 2015, and finalist for the National Instruments’ Engineering Impact Award 2017. He served as Editor-in-Chief of IEEE Std 1500 and as Founder and Chair (currently Vice-Chair) of the IEEE Std P1838 Working Group on 3D test access. Marinissen is founder of the workshops ‘Diagnostic Services in Network-on-Chips’ (DSNOC), DATE’s Friday 3D Integration, and the IEEE ‘International Workshop on Testing Three- Dimensional Integrated Circuits’ (3D-TEST). He has been Program Chair of DDECS 2002, ETS 2006, 3D-TEST 2009-15, and DATE 2013, and General Chair of ETW 2003, DSNOC 2007-08, 3DIW 2009-10, and serves on numerous conference committees, including ATS, DATE, ETS, ITC, ITC-Asia and VTS. He serves on the editorial boards of IEEE ‘Design & Test’ and Springer’s ‘Journal of Electronic  Testing: Theory and Applications’. During the span of his career, Marinissen has supervised 35 international MSc and PhD students, including two from NTHU. He is a Fellow of IEEE and Golden Core Member of Computer Society.




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